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FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase
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| Zeitschriftentitel: | International Journal of Computer Applications |
|---|---|
| Personen und Körperschaften: | |
| In: | International Journal of Computer Applications, 116, 2015, 17, S. 27-31 |
| Format: | E-Article |
| Sprache: | Unbestimmt |
| veröffentlicht: |
Foundation of Computer Science
|
| Schlagwörter: |
| author_facet |
Sharma, Abhay Sharma, Abhay |
|---|---|
| author |
Sharma, Abhay |
| spellingShingle |
Sharma, Abhay International Journal of Computer Applications FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase General Medicine |
| author_sort |
sharma, abhay |
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Sharma, Abhay 0975-8887 Foundation of Computer Science General Medicine http://dx.doi.org/10.5120/20430-2760 FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase International Journal of Computer Applications |
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Foundation of Computer Science, 2015 |
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Foundation of Computer Science, 2015 |
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0975-8887 |
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2015 |
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Foundation of Computer Science |
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International Journal of Computer Applications |
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49 |
| title |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_unstemmed |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_full |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_fullStr |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_full_unstemmed |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_short |
FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_sort |
fpga implementation of a high speed multiplier employing carry lookahead adders in reduction phase |
| topic |
General Medicine |
| url |
http://dx.doi.org/10.5120/20430-2760 |
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2015 |
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27-31 |
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International Journal of Computer Applications |
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| issn | 0975-8887 |
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| physical | 27-31 |
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| publisher | Foundation of Computer Science |
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| series | International Journal of Computer Applications |
| source_id | 49 |
| spelling | Sharma, Abhay 0975-8887 Foundation of Computer Science General Medicine http://dx.doi.org/10.5120/20430-2760 FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase International Journal of Computer Applications |
| spellingShingle | Sharma, Abhay, International Journal of Computer Applications, FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase, General Medicine |
| title | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_full | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_fullStr | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_full_unstemmed | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_short | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| title_sort | fpga implementation of a high speed multiplier employing carry lookahead adders in reduction phase |
| title_unstemmed | FPGA Implementation of a High Speed Multiplier Employing Carry Lookahead Adders in Reduction Phase |
| topic | General Medicine |
| url | http://dx.doi.org/10.5120/20430-2760 |